1/2 this is brief data from sgs-thomson. details are subject to change without notice for complete data, please contact your nearest sales office or smartcard products divison, rousset, france. fax: (+33) 4 42 25 87 29 ST14E32F st15e32f serial access extended addressing compatible with i 2 c bus 32k (4k x 8) eeprom brief data n compatible with i 2 c extended addressing n two wire serial interface, supports 400khz protocol n 100,000 erase/write cycles, over the full supply voltage range n 10 years data retention n single supply voltage C 4.5v to 5.5v for the ST14E32F C 2.7v to 5.5v for the st15e32f n write control feature n byte and page write (up to 32 bytes) n byte, random and sequential read modes n self timed programing cycle n automatic address incrementing n enhanced esd/latch up performances table 1 signal names figure 1 delivery forms figure 2 pin connection sda serial data address input output scl serial clock wc write control v cc supply voltage gnd ground module wafer scp 028 a/ai v cc gnd sda wc scl ST14E32F st15e32f 1 bd.32f/9609v1
2/2 ST14E32F st15e32f bd.32f/9609v1 description the st14/15e32f are 32k bit electrically erasable programmable memory products (eeprom), or- ganized as 8 blocks of 512 x 8 bits. the st15e32f circuit operates with a power supply value as low as 2.7v. the st14/15e32f are compatible with the i 2 c ex- tended addressing standard, two wire serial inter- face which uses a bi-directional data bus and se- rial clock. the st14/15e32f carry a built-in 4 bit, unique de- vice identification code (1010) corresponding to the i 2 c bus definition.the st14/15e32f behave as a slave device in the i 2 c protocol with all mem- ory operations synchronized by the serial clock. read and write operations are initiated by a start condition generated by the bus master. the start condition is followed by a stream of 4 bits (identification code 1010), 3 bit chip enable input to form a 7 bit device select, plus one read/ write bit and terminated by an acknowledge bit. when writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. when data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. data transfers are terminated with a stop condition. both wafers (sawn or unsawn) and micromodules (on film) are available. information furnished is believed to be accurate and reliable. however, sgs-thomson microe lectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics pro ducts are not a uthorized for use as critical components in life support devices or systems without the express written approval of sgs-thomson micr oelectro nics. ? 1997 sgs-thomson microelectro nics - printed in france - all rig hts r eserved purchase of i 2 c components by sgs-thomson micr oelectro nics conveys a licence under the philips i 2 c patent. right to use these components in an i 2 c system is granted pr ovided that the sy stem co nforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - c hina - france - germany - hong kong - i taly - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u. s.a.
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